1. Field of the Invention
This invention relates to a layout pattern for measuring the parameter of a device that is necessary for the simulation of a semiconductor device, especially a capacity measuring device and a capacity measuring method for measuring infinitesimal capacity.
2. Description of the Related Art
In the design of a semiconductor integrated circuit including LSI, simulation, such as the Simulation Program with IC Emphasis (SPICE), is used to evaluate the operational characteristics of a designed circuit. It is necessary that the parameter value of an individual transistor used as a model be close to the characteristic value of an actual transistor to obtain an accurate result in the simulation. Especially, the electrostatic capacity at the gate of a Metal Oxide Semiconductor (MOS) transistor has large influence on the transient response of the circuit. Accordingly, the accurately measured value is desired.
In the early years of the semiconductor integrated circuit with less miniaturization, it was possible to obtain a relatively accurate parameter by forming on an actual semiconductor substrate a layout for measuring capacity, which comprises a transistor pattern in full scale, a pad for contact with a measurement prober, and an extension metal for connecting the transistor and the pad, and measuring the layout pattern.
As the size of the transistor is made smaller with the miniaturization of the semiconductor device, the gate capacity of the transistor changed to the order of f(10−15)F from the order of p(10−12)F. However, the size of the measurement prober was unable to be proportionally miniaturized so that the minute capacity could not be measured. Consequently, the capacity measurement using the layout pattern comprising the transistor in full scale became impossible. Accordingly, as a new method, a layout pattern comprising a model transistor having a size a few hundreds larger than the actual transistor is measured and the measurement result is theoretically converted to obtain the parameter.
FIG. 2 is a top view of a conventional layout pattern for measuring the gate capacity.
The layout pattern is formed on a silicon substrate and comprises a transistor 1 having a size a few hundreds larger than that of the actual transistor. The transistor 1 is formed in a semiconductor well (not shown) and composed of a drain region 1d, a source region 1s, and a gate region 1g. A wiring pattern made of a metal film is formed on the surface of the silicon substrate, on which the transistor 1 is formed, via an insulating layer (not shown).
The wiring pattern is composed of an extension metal 2d and a pad 3d for a drain electrode, an extension metal 2s and a pad 3s for a source electrode, an extension metal 2g and a pad 3g for a gate electrode, and an extension metal 2w and a pad 3w for the well. The extension metals 2d, 2s, 2g, and 2w are electrically connected to the drain 1d, source 1s, and gate regions 1g, and the well, respectively, by contact metals via through-holes 4d, 4s, 4g, and 4w. 
For example, the pads 3d, 3s, and 3w are commonly connected to the ground GND and the electrostatic capacity between the pad 3g for the gate electrode and the ground GND is measured by using the above-described layout pattern. Then, the measured value is converted into the parameter for the simulation according to the proportion of the size of the pattern to that of the actual device.
However, the parameter obtained by the theoretical conversion according to the proportion of the sizes is different from the actual value, which causes the problem that the result of the simulation differs from the result of the measurement in the operation of the actual device.
Meantime, to solve the above problem, an infinitesimal capacity measuring system capable of measuring infinitesimal capacity of the order of fF has become known.
FIGS. 3(a)-3(c) show the infinitesimal capacity measuring system described in Japanese Patent Kokai No. 2000-55956.
As shown in FIG. 3(a), the infinitesimal capacity measuring system is composed of a prober 10 and a measuring circuit 20. The prober 10 comprises a shield case 11 having a stage 12, on which a device 30 to be measured is mounted, and coaxial cables 13 and 14 to be connected to the device 30. Probes are provided at the front ends of inside conductors 13a and 14a of the coaxial cables 13 and 14 such that they are brought into contact with any electrodes of the device 30 by manipulators 15 and 16.
Outside conductors 13b and 14b of the coaxial cables 13 and 14 are brought into contact with the shield case 11. The rear ends of the coaxial cables 13 and 14 extend outside the shield case 11 and are connected with the measuring circuit 20 and the ground potential GND, respectively. FIG. 3(b) shows the status of the connection between the device 30 and the coaxial cables 13 and 14 during the measurement. For example, the device 30 comprises a lower electrode 33 formed on a silicon substrate 31 via an insulating layer 32 and a measurement electrode 35 formed on the lower electrode 33 via an insulating layer 34. The front end of the inside conductor 13a of the coaxial cable 13 is brought into contact with the surface of the lower electrode 33 and the rear end of the coaxial cable 13 is connected to the measurement circuit 20. The front end of the inside conductor 14a of the coaxial cable 14 is brought into contact with the surface of the measurement electrode 35 and the rear end of the coaxial cable 14 is connected to the ground potential GND.
FIG. 3(c) is a schematic diagram of the capacity measuring circuit. The measurement electrode 35 of the device 30 is connected to the ground potential GND through the coaxial cable 14. The lower electrode 33 of the device 30 is led to the measurement circuit 20 through the inside conductor 13a of the coaxial cable 13 and connected to an inverting input terminal of an operational amplifier 21. The output side of the operational amplifier 21 is connected to an output terminal 22 and the inverting input terminal through a feedback resistor 23.
The outside conductor 13b of the coaxial cable 13 is connected to the non-inverting input terminal of the operational amplifier 21 without being connected to the ground potential GND. Also, an alternating current signal generator 24 is connected to the non-inverting input terminal of the operational amplifier 21.
In the above-described structure, conductive parts of the prober 10, such as the shield case 11, conductive parts of the stage 12, conductive parts of the manipulators 15 and 16, the rear surface of the silicone substrate 31, are connected to the non-inverting input terminal of the operational amplifier 21. On the other hand, an electrode of a measured capacity CX or the lower electrode 33 is connected to the inverting input terminal of the amplifier 21 through the coaxial cable 13. The other electrode of the measured capacity CX or measurement electrode 35 is connected to the ground potential GND through coaxial cable 14.
Negative feedback is loaded on the amplifier 21 through the feedback resistor 23, and since the open-loop voltage gain thereof is substantially infinite, the input side of the operational amplifier 21 is put in the state of imaginary short-circuit so that the difference of voltage between the inverting and non-inverting input terminals is substantially zero. When an AC signal having a voltage Vi and an angular frequency ω is applied to the non-inverting input terminal of the operational amplifier 21 from the AC signal generator 24, the output voltage Vo at the output terminal 22 is shown in the following formula (1):Vo=Vi(1+jωRf·Cx)  (1)wherein Rf is the resistance of the feedback resistor 23.
Accordingly, the measured capacity Cx can be calculated from the formula (1) by measuring the output voltage Vo.
Since the operational amplifier 21 is in the state of the imaginary short-circuit, the floating capacity which is considered to be produced between the inside and outside conductors 13a and 13b of the coaxial cable 13, such as a parasitic capacity produced in the shield case 11, is canceled. Accordingly, infinitesimal capacity of the order of fF can be measured.
That is, the above-described infinitesimal capacity measuring system, instead of the layout pattern shown in FIG. 2, makes it possible to measure the gate capacity of the layout pattern, in which a transistor is formed in an actual size. However, the conventional layout pattern for measuring the gate capacity has the following problem.
In FIG. 2, the size of the transistor 1 can be made as small as that of the actual transistor. However, the measurement pads 3d and 3g used for measurement of the electrostatic capacity between the electrodes of the transistor cannot be made small because of physical limitation of the measuring equipment. If only the transistor 1 is made small, the electrostatic capacity between the pads or the parasitic capacity is much larger than that of the electrostatic capacity between the electrodes of the transistor so that the electrostatic capacity between the electrodes cannot be accurately measured.